FIG. 1 shows a cross-sectional view of a MOS field effect transistor (FET) well known in the prior art. Such an MOS transistor typically includes source region 1s and drain region 1d, source extension region 2s and drain extension region 2d, channel 3, gate insulator 4 and gate 5. The source and drain regions 1s and 1d are heavily doped, typically with arsenic for n-type doping or boron for p-type doping. Doping levels are on the order of 1020 dopant atoms per cubic centimeter. The layers for regions 1s and 1d are typically 500-700 angstroms deep. The extension regions 2s and 2d are also heavily doped, with the same type of dopant atoms as the source and drain regions 1s and 1d, but the extension regions are shallower—typically 300 to 500 angstroms deep. FIGS. 2A and 2B show the doping profiles in the vertical and lateral directions (along the arrows A and B respectively in FIG. 1).
Extension regions 2s and 2d provide contact to the channel region 3. The transistor operates by applying a bias to the gate 5. For example, suppose the regions 1s, 2s, 2d and 1d are n-type, so that the majority carriers are electrons. If a positive voltage is placed on gate 5 with respect to the channel 3, no current will flow between the gate 5 and channel 3 because of the presence of thin gate insulator 4. However, the positive voltage will attract electrons to the gate region 3, creating a thin layer of electrons (called an inversion layer) that connects source extension 2s to drain extension 2d, allowing current to flow between the source and drain. When the voltage on gate 5 is removed, the inversion layer in channel 3 ceases to exist, and the source is disconnected from the drain. In this manner, the transistor can be turned on and off.
In practice, the doping profiles for the various source and drain layers 1s, 1d, 2s and 2d are not perfectly abrupt (box-like). They are usually formed by diffusion processes that may involve several thermal cycles, causing the profiles to be somewhat rounded. For example, FIG. 2A shows two profiles 11a and 11b for the source extension 2s, following arrow A in FIG. 1. Line 11a shows a relatively abrupt profile and line 11b shows a less abrupt profile. Such variation in abruptness (between lines 11a and 11b) may be encountered in different semiconductor wafers under fabrication because each step in the fabrication process has a certain tolerance. Variation in individual process steps or the cumulative variation of a series of process steps can cause a loss of abruptness in the profile (e.g. may go from line 11a to line 11b).
In addition, junction depth may vary depending on process properties, such as, for example, variation in annealing temperature. For example, profile 11b forms a deeper diffused profile than profile 11a. 
Similarly, the lateral profile shows a variation in abruptness depending on the tolerance of the individual process steps of semiconductor wafer fabrication. FIG. 2B shows the profile along arrow B in FIG. 1 (arrow B runs parallel to and just underneath the surface of the semiconductor wafer). Profiles 10sa and 10da (FIG. 2B) are more abrupt; profiles 10sb and 10db are less abrupt. In addition, profiles 10sb and 10db have diffused further, reducing the distance between the source and drain regions, and the length of channel 3. The degradation in lateral abruptness due to lateral diffusion is thought to be less severe than the corresponding degradation in vertical abruptness. However, the degradation in lateral abruptness or increase in lateral diffusion can have a greater effect on the performance of the transistor than the vertical abruptness degradation. Lateral and vertical abruptness degradations may also stem from different sources, so that a measure of one is not a measure of the other. For example, stress at the surface may enhance lateral diffusion of dopant atoms, an effect not seen in the vertical direction.
Lateral diffusion and abruptness must be carefully controlled because it directly affects the speed of the transistor and the ability of the transistor to drive the next stage in the circuit. Less lateral abruptness, as with profiles 10sb and 10db (FIG. 2B), causes the portion of the source and drain extensions 2a and 2b (FIG. 1) that contact the channel 3 to have lower doping and, hence, higher resistance. The degradation in lateral abruptness creates a series resistance component that leads to a greater voltage drop between the source 1s and drain 1d (FIG. 1). This voltage drop reduces the ability of the transistor to drive the next stage, reducing the speed of the circuit. Additionally, the lateral distance between the source and drain extensions, 2s and 2d, defines the length of the channel region 3. This channel length directly determines certain properties of the transistor, such as cutoff frequency.
Some of the prior art methods for measuring lateral diffusion (identified by how far the junction moves laterally during anneal) and abruptness (which is defined by the slope of the diffused profile) are electrical probing of transistors, capacitance atomic force microscopy (C-AFM), and inference from vertical secondary ion mass spectroscopy (SIMS) profiles.
Inference of lateral diffusion and abruptness is possible from electrical probing of transistors. This procedure requires contact to a full transistor structure. Consequently, electrical probing is impractical at the point in the process when the doped layers are being formed and the transistor is still incomplete. The time between the source/drain process steps and the first opportunity to probe can be days or weeks, greatly reducing the ability to implement real-time process control.
Probe methods such as C-AFM require sectioning of the transistor and various intermediate preparation steps. Even when this is complete, probing requires several hours, and the resolution is typically worse than 100 Å, too poor to provide an accurate measure of diffusion or abruptness for purposes of process control.
It is also possible to infer the lateral diffusion and abruptness from the vertical profile (of the type shown in FIG. 2A), assuming the lateral and vertical diffusion and abruptness relate to the same physical phenomena. However, methods such as SIMS are slow and destructive, and therefore not suited for routine in-line process control. In addition, as mentioned above, there may be certain cases where the lateral and vertical diffusion and abruptness do not fully relate to one another.